At power-up, a system having a flash memory has to determine a last written page address of the flash memory. In general, the system communicates with the flash memory through a controller. Currently, an erased page of a NAND flash memory is determined by the controller. A NAND flash memory sends data associated with a request page address to the controller, which determines whether or not the requested page is an erased page by counting the number of 1's or number of 0xFF patterns of the page. The data transfer of a selected page across the channel between the controller and the NAND flash memory is time consuming and adds additional time to the start-up process of the system.
In conventional operating systems, a host or a controller external to the flash memory is used to determine whether a page has been written to or whether it is available for new data. For example, software in the controller or host will read from the flash memory, determine an available page (i.e., an erased page) and store the available page as a target page in a temporary memory (or register). However, information in the temporary memory associated with the stored target page is lost when the controller (host) is powered down. At power up, the controller will have to determine the address of the last written page of the flash memory again. The determination of an available page is performed sequentially page per page until an available page is found. If not, then the controller has to read pages of the next block and continues the search process until an available page is found.
Other techniques may use binary search to locate an available page in a block. However, the binary-search approaches are time-intensive and consume channel bandwidth and power, resulting in overall poor performance of the system.
Thus, it is desirable to have a flash memory device and method that can determine the last written page without having the controller or host to perform time- and bandwidth-intensive processing.